Vhdl for Logic Synthesis: An Introductory Guide for Achieving Design Requirements

VHDL is the VHSIC Hardware Description Language,an industry standard language used to describe hardware from the abstract to the concrete level. It is embraced as the universal communication medium of design and computer-aided engineering workstation vendors throughout the industry are standardizing on VHDL as input and output from their tools. This book is aimed at hardware engineers with some experience of hardware design,but little or no experience in terms of the hardware mappings performed by synthesis. The book starts with a review of Register Transfer Level design,the foundation of logic synthesis. The basics of logic and registers are described first,then expanded by the effective use of types,including the proposed standard synthesisable types. More advanced techniques are developed,including the writing of packages and parametrisable modules. The book finishes with techniques for writing effective test benches. The concepts are illustrated throughout by examples,making it suitable as a source reference for synthesisable models.

This is the first book to detail the use of VHDL with logic synthesis techniques, showing how to use the hardware description language to achieve SLSI design results. It explains VHDL features in terms of the hardware mappings performed in synthesis basics, then builds to more advanced topics, like the writing of VHDL packages and the writing of effective text benches.